Programmable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), are user configurable ICs capable of implementing various digital logic operations. FPGAs include programmable logic circuits such as configurable logic blocks (CLBs) arranged in rows and columns, input/output blocks (IOBs) surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. The CLBs, IOBs, and interconnect lines are configured to implement a particular design according to configuration data stored in configuration memory cells of the programmable IC.
The versatility of programmable ICs is advantageous in applications, such as those requiring high availability, high reliability, or functional safety, where remote reconfiguration is preferred over physical replacement. However, with shrinkage of device geometry, atmospheric radiation can cause an error in a bi-stable circuit, which is known as a single event upset (SEU). When a single heavy ion strikes a silicon substrate, the ion loses energy through the creation of free electron hole pairs, resulting in a dense ionized track in the local region, and generating a current pulse that can upset the circuit. An SEU can also be caused by alpha particles. Alpha particles are generated when a neutron strikes a silicon substrate. The alpha particles travel through the substrate and generate charge clusters within a limited silicon volume. Alpha particles can be generated from high energy neutrons or from neutrons that have lost enough kinetic energy to be at thermal equilibrium with the operating environment. Alpha particles can also be generated through the decay of semiconductor packages that contain a small amount of radioactive contaminants.
In a programmable IC, an SEU may be of a configuration memory cell that is used to configure a programmable logic circuit. An SEU may additionally or alternatively induce errors by changing the value of a bi-stable circuit (e.g., a flip flop or latch) included in a user circuit design that is implemented by the programmable logic circuits. An error induced in configuration memory by an SEU may be referred to as a “configuration upset,” and an error induced in a bi-stable circuit of a user circuit design may be referred to as a logic upset.
Configuration and logic upsets induced by SEUs can be mitigated by implementing three redundant instances of a circuit along with a voting circuit to ensure that a correct value is output when a logic or configuration upset occurs in one of the redundant instances. A circuit having three redundant instances of a circuit and a voting circuit is said to implement “triple modular redundancy” (TMR).